High-density (HD) six-transistor (6T) single-fin FinFET SRAM bitcells that are fabricated using nanometer-scale CMOS fabrication technologies provide significant size and performance advantages over other SRAM bitcells formed using the same technologies. For example, HD 6T FinFET SRAM bitcells exhibit a 20-25% better bitcell area efficiency and lower leakage in comparison to High Performance (HP) SRAM bitcells, and exhibit 40-50% leakage advantage as compared to High Current (HC) SRAM bitcells. Accordingly, HD 6T FinFET SRAM arrays are currently preferred for use in current integrated circuit (IC) devices.
Memory assist circuitry (i.e., read-assist circuitry and/or write-assist circuitry) is typically utilized in HD SRAM arrays to address various read-ability and write-ability issues that arise in IC devices fabricated using nanometer scale fabrication technologies. For example, process variations that occur in nanometer scale fabrication technologies can cause the strength of the NMOS pull-up transistors used in 6T SRAM configurations to be much stronger than the strength of the PMOS pull-down transistors. As indicated by the table shown in FIG. 9, HD SRAM arrays including 7 nm FinFET High Density SRAM bitcells and operated at lower system voltages (i.e., below about 0.75V) exhibit stronger-NMOS/weaker-PMOS issues that can significantly degrade the bitcells' signal noise margin (SNM). Degradation of the write margin causes serious write-ability issues (i.e., the ability to accurately store “1” and “0” data bit values on HD 6T SRAM bitcells during write operations). Large Random variation on silicon also exhibit possibility of strong PMOS and weaker NMOS (SF Corner) that cause Degradation of the write margin and creates serious write-ability issues (i.e., the ability to accurately write “1” and “0” data bit values on HD 6T SRAM bitcells during write operations). To address write-ability issues, these HD SRAM arrays include write-assist circuitry configured to implement a suitable write-assist technique, such as lowering bitcell supply voltages, wordline boosting, negative bitline write, or implementing a body bias to improve the strength of NMOS pass-gate transistors relative to the strength of PMOS pull-up transistors. In addition, process variations and operating temperature variations can create an unacceptable SNM at lower voltages, which affects the read-ability of HD 6T SRAM bitcells (i.e., the ability to distinguish between “1” and “0” data bit values stored on the HD 6T SRAM bitcells during read operations). To address such read-ability issues, HD SRAM arrays include read-assist circuitry configured to implement a suitable read-assist technique such as using wordline lowering (also known as wordline under-drive (WLUD)), using higher bitcell supply voltages, using lower bitline capacitance, or modulating device characteristics using body bias.
The most commonly used read-assist technique utilized in HD SRAM FinFET arrays is wordline lowering (WLUD), where the asserted (high) voltage transmitted on a selected wordline (WL) of an HD SRAM array is pulled down (decreased or “lowered”) by the read-assist circuit to a WLUD voltage level that is lower than the SRAM array's high supply voltage (e.g., VDD). Lowering the voltage on a wordline when reading data from a 6T SRAM bitcell controlled by that wordline decreases the bitcell's pass-gate strength, which improves the read stability. FIGS. 10A and 10B include simplified diagrams depicting two conventional wordline lowering circuits, with the circuit shown in FIG. 10A using a PMOS read-assist transistor RA1 connected between an associated wordline W1 and system low voltage (ground) and controlled by way of connection to ground, and the circuit shown in FIG. 10B using a NMOS read-assist transistor RA2 connected between an associated wordline W2 and ground and controlled by a high supply voltage VDD. Each of these conventional read-assist circuits create a weaker current path through read assist transistors RA1 and RA2 that reduce (lower) the voltage level on wordlines W1 and W2 below the supply voltage level VDD during active read operations (i.e., when wordlines V1 and V2 are driven high by associated control circuitry). These wordline lowering read-assist approaches are often used during both read and write operations such that half-selected bitcells experience lower wordline voltages. However, lowering the wordline voltage during write operations degrades the write margin, so a write assist technique is usually implemented along with the wordline lowering technique approach.
Although the amount of wordline lowering produced by the conventional read-assist circuits shown in FIGS. 10A and 10B generates beneficially improved SNM during HD SRAM array read operations at higher operating temperatures, they are problematic at lower operating temperatures and Slow NMOS and Slow PMOS process (SS Corners), with operating frequency of SRAM Memory limited by performance achieved at SS/−40° C. That is, for ideal read assist schemes, the amount of wordline lowering (i.e., the “underdrive” or WLUD amount) is varied depending on process and temperature conditions, i.e., such that the lowest wordline voltage (highest amount of wordline lowering) occurs in the worst global corner for read stability (i.e., fast NMOS and slow PMOS, or “FS”), which occur at high operating temperatures, while the wordline voltage is maintained at a high level (i.e., lowest amount of wordline lowering) in other corners which are write-limited, which occur at lower operating temperatures. In conventional word line underdrive schemes (FIGS. 10A and 10B), the underdrive amounts at SS/−40° C. and SF/−40° C. corners are almost comparable to what is designed for FS/125° C. corners. This puts a performance penalty on memory. Considering similar degradation using these conventional wordline lowering schemes, cell current would have been reduced to one fourth, resulting into severe penalty on operating frequency and access time in the host SRAM array. That is, because SNM varies with process, voltage and temperature, it is important for a given read-assist circuit to vary the WLUD voltage such that wordline lowering is maximized at higher operating temperatures and minimized at lower operating temperatures. The conventional approaches depicted in FIGS. 10A and 10B fail to provide the needed temperature compensation.
Recently, temperature-compensated read-assist circuits have been proposed (e.g., as taught in U.S. Pat. No. 9,997,236) that utilize a NMOS read-assist transistor connected to each word line, temperature compensation circuitry configured to vary the gate voltage applied to the NMOS read-assist transistor such that more significant word line lowering occurs at higher temperatures than at lower temperatures. Typically, the process for SRAM (Bitcell) and Periphery (i.e., control circuity+Word line PMOS+Read circuit assist circuitry) are not aligned. In low nodes as fabrication mask for SRAM and logic are not same (e.g., SRAM bitcell might have faster PMOS and slow NMOS while word line and read assist schemes might have Slower NMOS and faster PMOS, and vice versa). In misaligned variation across SRAM and periphery process, lowering word line though NMOS is not a robust scheme and will lower yield finally increasing SOC cost.
What is needed is a read-assist circuit that exhibits improved temperature tracking capabilities independent of process while avoiding the SRAM and periphery alignment constraints.